Donn's Website

Portfolio

This is a list of projects I've worked on that I consider particularly significant.

Fault (June 2019-)

Fault is an open source automatic test pattern generator for the stuck-at fault model. It's written in Swift with Tensorflow's Python interoperability layer.

Fault was published on IEEE Design & Test! It also won 4th place at the Workshop on Open Source EDA Technologies, part of the 2019 International Conference On Computer Aided Design, Westminster, Colorado, which is cool I guess. (Paper)

Fault is available at its GitHub repository.

Phi (September 2018-)

Phi is a hardware description language inspired by Verilog that focuses on a pure register transfer level design paradigm. Designed out of general frustration with Verilog, Phi is syntactically closer to modern C-style languages with a subset of Verilog's semantics (and some additions).

The reference compiler is about 70%? done, it is available at its GitHub repository, alongside the language's specifications and paper.

Oak (August 2016)

Oak is an extensible assembler, disassembler and simulator toolchain written in TypeScript. I initially wrote it in Swift to try to learn assembly language programing, but then decided against it after the TypeScript version somewhat caught on. We also tried a cycle-accurate version, a veritable dumpster fire available on one of my partners' GitHub page.

Oak runs entirely in your web browser, so you can try it out right now! It supports RISC-V and MIPS.

The full source code is available under the Mozilla Public License 2.0 over at its GitHub repository. The Swift version's source code is also available here, but why do you need that?

Beekeeper (February 2017)

Beekeeper is a co-simulation framework for use with Verilog simulators. It allows hardware-accurate debuggers to be written in a modular fashion and integrates with the Cloud V SoC editor so that users may test their SoCs entirely in software. It's been since cancelled for a number of reasons.

RiscBEE (December 2016)

A single-cycle RISC-V RV32i computer implemented in Verilog for the Digilent Nexys 3 board, by the same team as Oak.js (i.e. myself and @KarimIO,) and the first project to started the unmitigated blizzard of bee references in my hardware project names. It runs at ~50MHz, supports basic memory-mapped I/O and completely unaligned memory access. Also has a pretty cool parameterized multiplexer-based barrel shifter. Neat stuff.

It's available over at its GitHub repository.

attend (July 2016)

attend is an app that records attendance only using technologies that already exist in the classroom working in tandem with a web server and a Gmail account. Using QR codes that are presented via the classroom projector and attendee's smartphones, attendees have but to open the app and point their iPhone, iPad or Android device at the projected QR code and their attendance is recorded.

The program includes a system for scheduling events, controlling QR code generation/attendance validity, excusing absences, a web UI for more mundane administrative tasks, enrolling students that have not yet registered for the service, and many, many more features.

Of course, this idea has been implemented multiple times since but such is life. Still glad to be the first.

attend's full source code is available in its dedicated GitHub repository under a permissive license.